-- VHDL Code of 8251 Unit , UART
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity CS_8251_UNIT is
	generic(
			  REG_8BIT_SIZE : positive := 8			 
		  );
	port(
		   -- Data Bus Buffer
		   D         : inout std_logic_vector(REG_8BIT_SIZE - 1 downto 0);
		   -- Write/Read Control Logic
		   RST        : in    std_logic;
		   CLK        : in    std_logic;
		   C_N_D      : in    std_logic;
		   RD_N       : in    std_logic;
		   WR_N       : in    std_logic;
		   CS         : in    std_logic;		
		   -- Modem Control
		   DSR_N      : in    std_logic;
		   DTR_N      : out   std_logic;
		   CTS_N      : in    std_logic;
		   RTS_N      : out   std_logic;
		   -- Transfer Buffer
		   TxD        : out   std_logic;
		   -- Transfer Control
		   TxRDY      : out   std_logic;
		   TxEMPTY    : out   std_logic;
		   TxC_N      : in    std_logic;
		   -- Receive Buffer
		   RxD        : in    std_logic;
		   -- Receive Control
		   RxRDY      : out   std_logic;
		   SYNDET_BRK : out   std_logic;
		   RxC_N      : in    std_logic
	    );
end CS_8251_UNIT;
architecture CS_8251_UNIT_arch of CS_8251_UNIT is
begin
end CS_8251_UNIT_arch;